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[VHDL-FPGA-Verilog] multi-CPU

Description: Verilog开发的能下载到FPGA实验板上运行的多周期CPU-Verilog can be downloaded to the FPGA development board running experiments multi-cycle CPU
Platform: | Size: 2049024 | Author: gtx | Hits:

[File Format] CPU

Description: 基于FPGA控制的ASIC CPU系统设计，全是用VERILOG代码编写，可以做加减乘除运算 -FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
Platform: | Size: 1844224 | Author: xiaokai | Hits:

[VHDL-FPGA-Verilog] FPGA_CPU

Description: FPGA VERILOG CPU ASIC cpu芯片设计-FPGA VERILOG CPU
Platform: | Size: 468992 | Author: 董辉辉 | Hits:

[VHDL-FPGA-Verilog] Verilog-language--de-CPU

Description: 基于verilog语言的FPGA开发，平台在QuartusII上，对SDRAM的读写-Verilog language based FPGA development platform on QuartusII, the SDRAM read and write
Platform: | Size: 41984 | Author: 宋雪涛 | Hits:

[Other] 88RISC-CPU

Description: cpu设计能在quartus上运行 用verilog语言-a cpu program use verilog on quartus
Platform: | Size: 4400128 | Author: 倪歌 | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPSCPU

Description: 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
Platform: | Size: 169984 | Author: zhql945 | Hits:

[SCM] cpu

Description: Verilog代码，支持IO，中断的cpu实现。-Verilog code, support IO, interrupt cpu implementation.
Platform: | Size: 12288 | Author: lslifediyi | Hits:

[VHDL-FPGA-Verilog] cpu

Description: verilog 8 bit cpu working condition but need minor modification
Platform: | Size: 10240 | Author: shobhit | Hits:

[VHDL-FPGA-Verilog] 8-bit-CPU

Description: This is a simple 8-bit CPU verilog source code,which includes user s guide.
Platform: | Size: 2576384 | Author: Yan Tian | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
Platform: | Size: 12288 | Author: 胡森 | Hits:

[Windows Develop] CPU(4)

Description: 基于ISE XILINX14.7开发的单周期CPU的基础指令实现代码 VERILOG-VERILOG implementation code base based on single-cycle instruction CPU ISE XILINX14.7 development of
Platform: | Size: 605184 | Author: 泡温泉 | Hits:

[ARM-PowerPC-ColdFire-MIPS] cpu-7-verilog

Description: 多周期cpu设计asadsdddasd-multi cpu design
Platform: | Size: 1024 | Author: 李杰 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
Platform: | Size: 7168 | Author: 耿瑞 | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU

Description: 用Verilog实现的 哈佛结构的简单指令集CPU程序，由ALU、地址译码器、指令译码器等部分组成-Part of a simple instruction Verilog realize the Harvard architecture CPU program set by the ALU, address decoder, an instruction decoder, etc.
Platform: | Size: 4096 | Author: qiaozhitong | Hits:

[VHDL-FPGA-Verilog] Implement-a-CPU

Description: 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU-Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
Platform: | Size: 3118080 | Author: 骆扬 | Hits:

[VHDL-FPGA-Verilog] Zet-1.3.1

Description: 在单片FPGA上实现九十年代初期PC，可安装Windows3.1及其他DOS系统。SOC中包含以80286(cpu),中断控制器,显示控制器(VGA),声音控制器,PS2(鼠标，键盘)等。是了解计算机历史变迁及学习SOC设计的重要资料！(ZET aims to implement an early 90`s PC on FPGA.Which include a 80286(cpu),interrupt controller,display card(VGA),sound card,PS2 interface .)
Platform: | Size: 2487296 | Author: VectorIII | Hits:

[VHDL-FPGA-Verilog] mips

Description: mips verilog进行编写cpu,其中包括了若干的基本指令(use the verilog language to programme the CPU)
Platform: | Size: 4096 | Author: 光亮 | Hits:

[VHDL-FPGA-Verilog] MCPU

Description: 多周期CPU的verilog代码，用vivado可以仿真出波形(multi-cycle CPU by verilog and using vivado to simulate.)
Platform: | Size: 5875712 | Author: Lsinger | Hits:

[VHDL-FPGA-Verilog] 8051-master

Description: 设计兼容51的指令集的处理器架构 编写兼容51处理器的Verilog代码 仿真 验证测试处理器的功能和性能(The design includes a processor whose instruction set is compatible to the industrial standard 8051 and its FPGA implementation. Through the analysis of instructions, I determine the CPU internal data path, and according to the data path and the timing of the functional modules, I design the CPU controller, thus completing the design of the CPU core. Writing the module code in Verilog language and running the lighting program on DE2, I validate and test the related functions and performance.)
Platform: | Size: 13230080 | Author: PhoebeBNN | Hits:

[Other] CPU

Description: 语言为verilog，平台是ISE，指令较少。32位MIPScpu，可以直接运行(The language is Verilog, the platform is ISE, and the instructions are fewer. 32 bit MIPScpu, can run directly)
Platform: | Size: 1955840 | Author: 万寿吾江1 | Hits:
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